ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Browse by Author

Up a level
Export as [feed] Atom [feed] RSS 1.0 [feed] RSS 2.0
Group by: Item Type | No Grouping
Number of items: 28.

Conference Paper

Das, Pratap Kumar and Bharadwaj, Amrutur and Sridhar, J and Visvanathan, V (2008) On-Chip Clock Network Skew Measurement using Sub-Sampling. In: 4th IEEE Asian Solid-State Circuits Conference, NOV 03-05, 2008, Fukuoka, Japan.

Nandy, SK and Ramanathan, S and Visvanathan, V (2002) Synthesis of configurable architectures for DSP algorithms. In: 12th International Conference on VLSI Design, 7-10 Jan 1999, Goa , India.

Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Synthesis of Congurable Architectures for DSP Algorithms. In: Twelfth International Conference On VLSI Design, 1999, 7-10 January, Goa,India, pp. 350-357.

Mandal, Pradip and Visvanathan, V (1999) A new Approach for CMOS Op-Amp Synthesis. In: Twelfth International Conference On VLSI Design, 1999, 7-10 January, Goa,India, 189 -194.

Ramanathan, S and Visvanathan, V (1997) Low-Power Configurable Processor Array for DLMS Adaptive Filtering. In: Tenth International Conference on VLSI Design, 1997, 4-7 January, Hyderabad,India, 198 -203.

Mandal, Pradip and Visvanathan, V (1997) A Self-Biased High Performance Folded Cascode CMOS Op-Amp. In: Tenth International Conference on VLSI Design, 1997, 4-7 January, Hyderabad,India, 429 -434.

Ramanathan, S and Visvanathan, V (1996) A Systolic Architecture for LMS Adaptive Filtering with Minimal Adaptation Delay. In: Ninth International Conference on VLSI Design, 1996, 3-6 January, Bangalore,India, pp. 286-289.

Visvanathan, V and Ramanathan, N (1995) A modular systolic architecture for delayed least mean squares adaptive filtering. In: of the 8th International Conference on VLSI Design, 4-7 Jan. 1995, New Delhi, India, pp. 332-337.

Anuradha, VK and Visvanathan, V (1994) A CORDIC Based Programmable DXT Processor Array. In: Seventh International Conference on VLSI Design, 1994, 5-8 January, Kolkata, pp. 343-348.

Giri, A and Visvanathan, V and Nandy, SK and Ghoshal, SK (1994) High Speed Digital Filtering on SRAM-based FPGAs. In: Seventh International Conference on VLSI Design, 1994, 5-8 January, Kolkotta,India, 229 -232.

Visvanathan, V and Ramanathan, S (1994) Synthesis of energy-efficient configurable processor arrays. In: First International Workshop on Parallel Processing:IWPP'94, 26-31 December 1994, Bangalore, India, pp. 627-632.

Somasekhar, Dinesh and Visvanathan, V (1993) A 23Q MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking. In: Sixth International Conference on VLSI Design, 1993, 3-6 January, Bombay,India, 347 -350.

Visvanathan, V and Mohanty, Nibedita and Ramanathan, S (1993) An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. In: Sixth International Conference on VLSI Design,1993, 3-6 January, Bombay,India, pp. 166-171.

Mandal, Pradip and Visvanathan, V (1993) Macromodeling of the A.C. Characteristics of CMOS Op-Amps. In: 1993 IEEE/ACM International Conference on Computer-Aided Design, ICCAD-93. Digest of Technical Papers, 7-11 November, Santa Clara,California, 334 -340.

Ghosh, Debabrata and Nandy, SK and Parthasarathy, K and Visvanathan, V (1993) NPCPL : Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. In: The Sixth International Conference on VLSI Design,1993, 3-6 January, Bombay,India, pp. 341-346.

Nandy, SK and Narayanan, R and Visvanathan, V and Sadayappan, P and Chauhan, PS (1993) A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. In: 1993 International Conference on Parallel Processing, AUG 16-20, 1993, SYRACUSE UNIV, SYRACUSE, NY,.

Conference Poster

Das, Bishnu Prasad and Amrutur, Bharadwaj and Jamadagni, HS and Arvind, NV and Visvanathan, V (2008) Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator. In: Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, 21-24 Sept. 2008, San Jose, CA, pp. 133-136.

Journal Article

Das, Bishnu Prasad and Amrutur, Bharadwaj and Jamadagni, HS and Arvind, NV and Visvanathan, V (2011) Voltage and Temperature-Aware SSTA Using Neural Network Delay Model. In: IEEE Transactions on Semiconductor Manufacturing, 24 (4). pp. 533-544.

Janakiraman, V and Bharadwaj, Amrutur and Visvanathan, V (2010) Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29 (7). pp. 1056-1069.

Das, Bishnu Prasad and Amrutur, Bharadwaj and Jamadagni, HS and Arvind, NV and Visvanathan, V (2009) Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator. In: IEEE Transactions on Semiconductor Manufacturing, 22 (2). pp. 256-267.

Mandal, Pradip and Visvanathan, V (2001) CMOS Op-Amp Sizing Using a Geometric Programming Formulation. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20 (1). pp. 22-38.

Ramanathan, S and Nandy, SK and Visvanathan, V (2000) Reconfigurable Filter Coprocessor Architecture for DSP Applications. In: The Journal of VLSI Signal Processing, 26 (3). pp. 333-359.

Ramanathan, S and Visvanathan, V and Nandy, SK (1999) A computational engine for multirate FIR digital filtering. In: Signal Processing, 79 (2). pp. 213-222.

Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. In: Journal of VLSI Signal Processing, 22 (3). pp. 173-195.

Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Synthesis of ASIPs for DSP algorithms. In: Integration, the VLSI Journal, 28 (1). 13-32 .

Mandal, Pradip and Visvanathan, V (1999) Active biasing of multistage CMOS op-amps for performance enhancement. In: International Journal of Electronics, 86 (8). pp. 933-946.

Ramanathan, S and Visvanathan, V (1999) Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay. In: Integration, the VLSI Journal, 27 (1). pp. 1-32.

Somasekhar, Dinesh and Visvanathan, V (1993) A 230-MHz Half-Bit Level Pipelined Multiplier Using True Single-Phase Clocking. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1 (4). pp. 415-422.

This list was generated on Fri Nov 28 09:23:18 2014 IST.